FUNDAMENTALS OF VERILOG HDL DESIGN AND SYNTHESIS -A GUIDE TO SIMULATE DIGITAL CIRCUITS

This book covers the use of Verilog Hardware Description Language (HDL) basics for design and implementation of digital circuits. The popular and widely used Verilog HDL is introduced and applied to the description and verification of digital designs.

​As the size and complexity of digital systems increase, more and more computer aided design tools are being introduced into the hardware design process. The early paper and pencil design methods have given way to sophisticated design entry, verification and automatic hardware generation tools. In the design process much of the work of transforming a design from one form to another is tedious and repetitive. Design automation tools will help the designer for design entry, hardware generation and verification and design management.

Hardware Description Languages [HDLs] are used to describe hardware for the purpose of Simulation, Modeling, Testing, Design and Documentation of digital systems. The most popular HDLs are VHDL [(Very High Speed Integrated Circuit) Hardware Description Language] and Verilog. In the early 60’s there was discreet logic. Systems were built from lots of individual chips with a spaghetti-like maze of wiring between them. It was difficult to modify such systems after they were built. Manufacturing such systems took lot of time, because each design change required that the wiring be redone, which usually meant building a new printed circuit board. This problem was solved by placing an unconnected array of AND-OR gates in a single chip called as Programmable Logic Devices (PLDs).